Conventionally, liquid crystal display devices that are provided with a memory circuit for each pixel, which is the smallest unit of an image, and that perform binary memory display, in addition to a normal full color display in which still images and videos are displayed in multiple gradations, have been known (see Patent Document 1, for example). In the binary memory display, a data potential written in the pixel is maintained by the memory circuit, and still images are displayed by performing a refresh operation while reversing the polarity of the data potential.
In such a liquid crystal display device, during the period of the binary memory display, the data potential stored in the memory circuit is used, and therefore, it is not necessary to supply new data potential to each pixel. Because this allows all of peripheral driver circuits, except for an AC driver circuit performing the refresh operation, to be stopped, power consumption can be reduced. Therefore, this liquid crystal display device can be suitably used as a display device for performing image display in which a reduction in power consumption is strongly demanded such as standby screen display in mobile phones.
Each pixel of the above-mentioned liquid crystal display device that can perform binary memory display includes: a drive control TFT connected to a gate wiring line and a source wiring line; a pixel potential capacitance element and a pixel electrode connected to the drive control TFT; and the memory circuit described above. The memory circuit is provided with: an input control TFT that controls an input of a binary logic level, which is high (active level) or low (non-active level); a memory capacitance element that stores the binary logic level inputted through the input control TFT; an inverter circuit as a control circuit that determines a binary logic level to be outputted to the outside based on the binary logic level stored in the memory capacitance element; and an output control TFT that controls an output of a binary logic level with the polarity reversed by the inverter circuit, to the pixel potential capacitance element and the pixel electrode. The inverter circuit is constituted of an n-type TFT and a p-type TFT each having the gate connected to the memory capacitance element. The source of the n-type TFT is applied with a low potential, and the source of the p-type TFT is applied with a high potential. The drains of these n-type TFT and p-type TFT are integrally formed with each other and connected to the source of the output control TFT. The drive control TFT, the input control TFT, the n-type TFT and p-type TFT of the inverter circuit, and the output control TFT are all formed on a base substrate having an insulating property such as a glass substrate.
When the liquid crystal display device configured in the manner described above performs the binary memory display, first, a data potential of a binary logic level (high, for example) is written into the pixel potential capacitance element and the pixel electrode. Next, the input control TFT is turned on, and the data potential of the pixel potential capacitance element is inputted and stored in the memory capacitance element. The potential of the binary logic level stored in the memory capacitance element is converted into a reverse potential (low, for example) with the polarity reversed by the inverter circuit as a result of one TFT (n-type TFT, for example) of the inverter circuit being turned on and the other TFT (p-type TFT, for example) being turned off, based on the potential. Then, the output control TFT is turned on such that the reverse potential is inputted and stored in the pixel potential capacitance element and the pixel electrode. This way, the potential of the pixel potential capacitance element and the pixel electrode is refreshed to the reverse potential. By repeating such a refresh operation, a still image can be displayed while preventing the degradation of the data potential in the pixel potential capacitance element and the pixel electrode.